1. Technical Field
The present invention relates to a method of self-aligning a trench isolation structure to an implanted well region.
2. Background Art
The trend of the semiconductor industry is toward smaller more densely packed Very Large Scale Integrated Circuits (VLSIC). As devices become smaller and more densely packed, device interreactions become more of a common occurrence and concern. Many different approaches have been proposed for providing electrical isolation between neighboring semiconductor devices.
The isolation approach to which the present invention is directed is the use of isolation trench structures which are aligned to the perimeter of an implanted well region. In FIG. 1, there is shown a cross sectional view of an implanted semiconductor device provided with isolation trench structures.
More particularly, there is shown a doped or implanted well region 110 formed in a semiconductor substrate body 100. For the purpose of this application, the implanted well region 110 is a generic representation which represents a region utilized in any of numerous semiconductor devices, for example, a bipolar transistor, an FET transistor or a diode. Formed at the periphery of the implanted well region 110 are isolation trenches 120 and 130 which are filled with an insulator material 140. Each of the isolation trenches 120 or 130, filled with the insulator material 140, represents an isolation trench structure or barrier which isolates the implanted well region from neighboring implanted well regions or devices. Any of the insulator materials well known in the semiconductor art can be used, one suitable example being silicon dioxide.
It should be noted that FIG. 1 represents an ideal arrangement; i.e., where the isolation trench structures are perfectly aligned to the perimeter of the implanted well region, and where the whole of the semiconductor substrate area between these isolation structures is efficiently doped at an optimum doping concentration.
Turning now to FIGS. 2A-2C, there is shown a prior art approach directed toward fabricating the above trench isolation arrangement. In this prior art approach, two maskings steps are utilized to fabricate the resulting structure. In the first processing step of FIG. 2A, a first resist layer 210 is formed on the top surface of a semiconductor substrate body 200. The first resist layer 210 has been patterned in accordance with a first mask to provide an aperture 220 which is used to facilitate doping of the implanted well region 230 into the semiconductor substrate body 200.
Once implanted, the first resist layer 210 is removed, and a second resist layer is formed on the top surface of the semiconductor substrate body 200. This second resist layer 240, as shown in FIG. 2B, is then patterned in accordance with a second mask to provide the trench apertures 250 and 260 which are used to etch isolation trenches 270 and 280 into the semiconductor substrate body 200. Once formed, the second resist 240 is removed, and the isolation trenches 270 and 280 are filled with an insulator material 290. The result of these processing steps is an implanted well region 230 with corresponding isolation trench structures as shown in FIG. 2C.
In addition to showing the processing steps, FIGS. 2A-2C also illustrate shortcomings of this prior art approach. The first of these shortcomings results from the use of a two-mask approach. As can be seen in FIGS. 2B and 2C, any misalignment of the first and second mask will result in misalignment of the isolation trench structures with the corresponding implanted well region. This misalignment is disadvantageous in at least two respects. First, a portion of the implanted well region 230 is caused to lie or stray outside the isolation region. This stray implantation may very well interfere with neighboring devices. Second, a portion of the isolation region is at a less than optimum doping concentration, thereby producing an inefficient use of semiconductor substrate area. As a another shortcoming, there is a further inefficient use of semiconductor substrate area due to large widths of the isolation structures. This large width is caused by the limitations associated with using a photolithography masking technique to define the trench apertures.
As a result of the deficiencies in the prior art, there has long existed a need for a processing approach which offers greater guarantees that an isolation trench structure will be self-aligned to the implanted well region, that no stray implantation regions will be formed outside of the isolation region, and that the semiconductor substrate area between the isolation structures will be doped to an optimum doping concentration. Furthermore, there has long existed a need for a processing approach which produces narrow isolation trench structures.